Ok, let’s talk about one of the tips for writing Makefile, the magic character ‘@’
Before continue, let’s think about one thing: when you want to build a project, write a shell script or use the Make for building your project, which one would you prefer?
Ok, I’ll choose Make, the reasons are:
- The shell script may contain the code which is specific for the target shell, for example: bash. So, if some users DO NOT use bash, the build process may stop unexpected. And the Make is stand alone, which can run on all UNIX like system, not depend on a specific shell environment.
- You need to handle all the building actions, for example, entry the target folder, return back to last folder, do the dependence actions before actual do the building actions, etc, and the Make has already supported all of the above.
If you agree with me, follow me to the next step — Using ‘@’ in your Makefile.
Let’s take a look at a example Makefile:
all: echo "hello Makefile"
When we run it, the output is:
bash $ make echo "hello Makefile" hello Makefile
From above, we can see the original instructions are shown as well, they are useless and not beautiful, so let’s using ‘@’ to rewrite the Makefile:
all: @echo "hello Makefile"
And run it again:
bash $ make hello Makefile
From above, we can see the original instructions(echo xxx) have gone, it only shows the output of this command. So if you build a very large project, it may contain a lot of instructions, in this way you can using ‘@’ to avoid outputing the command, only show its result.
Reference: https://github.com/finaldie/final_dev_env/blob/master/Makefile